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5.5 Internal clocking requirements
The clock dividers are programmed via the SIM module’s CLKDIV registers. Each
divider is programmable from a divide-by-1 through divide-by-16 setting. The following
requirements must be met when configuring the clocks for this device:
1. The core and system clock frequencies must be 72 MHz or slower.
2. The bus clock frequency must be programmed to 50 MHz or less and an integer
divide of the core clock.
3. The flash clock frequency must be programmed to 25 MHz or less, less than or equal
to the bus clock, and an integer divide of the core clock.
4. The FlexBus clock frequency must be programmed to be less than or equal to the bus
clock frequency.
The following are a few of the more common clock configurations for this device:
Option 1:
Clock Frequency
Core clock 50 MHz
System clock 50 MHz
Bus clock 50 MHz
FlexBus clock 50 MHz
Flash clock 25 MHz
Option 2:
Clock Frequency
Core clock 72 MHz
System clock 72 MHz
Bus clock 36 MHz
FlexBus clock 36 MHz
Flash clock 24 MHz
5.5.1 Clock divider values after reset
Each clock divider is programmed via the SIM module’s CLKDIVn registers. The flash
memory's FTFL_FOPT[LPBOOT] bit controls the reset value of the core clock, system
clock, bus clock, and flash clock dividers as shown below:
Chapter 5 Clock Distribution
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
167
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