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5.7.3 Debug trace clock
The debug trace clock source can be clocked as shown in the following figure.
SIM_SOPT2[TRACECLKSEL]
TRACECLKIN
Core / system clock
MCGOUTCLK
Debug
Figure 5-3. Trace clock generation
5.7.4 PORT digital filter clocking
The digital filters in each of the PORTx modules can be clocked as shown in the
following figure.
NOTE
In stop mode, the digital input filters are bypassed unless they
are configured to run from the 1 kHz LPO clock source.
PORTx_DFCR[CS]
PORTx digital input
filter clock
Bus clock
LPO
Figure 5-4. PORTx digital input filter clock generation
Chapter 5 Clock Distribution
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
171
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