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NOTE
The MCGFLLCLK does not meet the USB jitter specifications
for certification.
5.7.7 FlexCAN clocking
The clock for the FlexCAN's protocol engine can be selected as shown in the following
figure.
CANx_CTRL1[CLKSRC]
FlexCAN clock
Bus clock
OSCERCLK
Figure 5-7. FlexCAN clock generation
5.7.8 UART clocking
UART0 and UART1 modules operate from the core/system clock, which provides higher
performance level for these modules. All other UART modules operate from the bus
clock.
5.7.9 I
2
S/SAI clocking
The audio master clock (MCLK) is used to generate the bit clock when the receiver or
transmitter is configured for an internally generated bit clock. The audio master clock can
also be output to or input from a pin. The transmitter and receiver have the same audio
master clock inputs.
Each SAI peripheral can control the input clock selection, pin direction and divide ratio
of one audio master clock.
Chapter 5 Clock Distribution
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
173
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