Information

The I
2
S/SAI transmitter and receiver support asynchronous bit clocks (BCLKs) that can
be generated internally from the audio master clock or supplied externally. The module
also supports the option for synchronous operation between the receiver and
transmitterproduct.
The transmitter and receiver can independently select between the bus clock and the
audio master clock to generate the bit clock.
The MCLK and BCLK source options appear in the following figure.
Fractional
Clock
Divider
1
0
11
01
10
00
OSC0ERCLK
MCGPLLCLK
SYSCLK
I2Sx_MCR[MOE]
MCLK
MCLK_OUT
MCLK_IN
11
01
10
00
BUSCLK
[MSEL]
Bit
Clock
Divider
1
0
BCLK_IN
I2S/SAI
BCLK_OUT
[BCD]
BCLK
I2Sx_MDR[FRACT,DIVIDE]
I2Sx_MCR[MICS]
Clock Generation
[DIV]
I2Sx_TCR2/RCR2
Figure 5-8. I
2
S/SAI clock generation
5.7.10 TSI clocking
In active mode, the TSI can be clocked as shown in the following figure.
TSI_SCANC[AMCLKS]
TSI clock
in active mode
Bus clock
MCGIRCLK
OSCERCLK
Figure 5-9. TSI clock generation
In low-power mode, the TSI can be clocked as shown in the following figure.
NOTE
In the TSI chapter, these two clocks are referred to as LPOCLK
and VLPOSCCLK.
Module clocks
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
174
Preliminary
Freescale Semiconductor, Inc.
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