Information

Table 7-2. Module operation in low power modes (continued)
Modules Stop VLPR VLPW VLPS LLS VLLSx
EzPort disabled disabled disabled disabled disabled disabled
Communication interfaces
USB FS/LS static static static static static OFF
USB DCD static FF FF static static OFF
USB Voltage
Regulator
optional optional optional optional optional optional
UART static, wakeup
on edge
125 kbps 125 kbps static, wakeup
on edge
static OFF
SPI static 1 Mbps 1 Mbps static static OFF
I
2
C static, address
match wakeup
100 kbps 100 kbps static, address
match wakeup
static OFF
CAN wakeup 256 kbps 256 kbps wakeup static OFF
I
2
S FF with external
clock
5
FF FF FF with external
clock
5
static OFF
Security
CRC static FF FF static static OFF
Timers
FTM static FF FF static static OFF
PIT static FF FF static static OFF
PDB static FF FF static static OFF
LPTMR FF FF FF FF FF FF
RTC - 32kHz
OSC
4
FF FF FF FF FF
6
FF
6
CMT static FF FF static static OFF
Analog
16-bit ADC ADC internal
clock only
FF FF ADC internal
clock only
static OFF
CMP
7
HS or LS level
compare
FF FF HS or LS level
compare
LS level
compare
LS level
compare
6-bit DAC static FF FF static static static
VREF FF FF FF FF static OFF
12-bit DAC static FF FF static static static
Human-machine interfaces
GPIO wakeup FF FF wakeup static, pins
latched
OFF, pins
latched
TSI wakeup FF FF wakeup wakeup
8
wakeup
8
1. Using the LLWU module, the external pins available for this chip do not require the associated peripheral function to be
enabled. It only requires the function controlling the pin (GPIO or peripheral) to be configured as an input to allow a
transition to occur to the LLWU.
2. A 16KB portion of SRAM_U block is left powered on in low power mode VLLS2.
3. FlexRAM enabled as EEPROM is not writable in VLPR and writes are ignored. Read accesses to FlexRAM as EEPROM
while in VLPR are allowed. There are no access restrictions for FlexRAM configured as traditional RAM.
4. These components remain powered in BAT power mode.
5. Use an externally generated bit clock or an externally generated audio master clock (including EXTAL).
Chapter 7 Power Management
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
195
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