Information

121
MAP
BGA
100
LQFP
Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 EzPort
E5 40 VDD VDD VDD
G3 41 VSS VSS VSS
K8 42 PTA12 CMP2_IN0 CMP2_IN0 PTA12 CAN0_TX FTM1_CH0 I2S0_TXD0 FTM1_QD_
PHA
L8 43 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX FTM1_CH1 I2S0_TX_FS FTM1_QD_
PHB
K9 44 PTA14 DISABLED PTA14 SPI0_PCS0 UART0_TX I2S0_RX_
BCLK
I2S0_TXD1
L9 45 PTA15 DISABLED PTA15 SPI0_SCK UART0_RX I2S0_RXD0
J10 46 PTA16 DISABLED PTA16 SPI0_SOUT UART0_CTS_
b/
UART0_COL_
b
I2S0_RX_FS I2S0_RXD1
H10 47 PTA17 ADC1_SE17 ADC1_SE17 PTA17 SPI0_SIN UART0_RTS_
b
I2S0_MCLK
L10 48 VDD VDD VDD
K10 49 VSS VSS VSS
L11 50 PTA18 EXTAL0 EXTAL0 PTA18 FTM0_FLT2 FTM_CLKIN0
K11 51 PTA19 XTAL0 XTAL0 PTA19 FTM1_FLT0 FTM_CLKIN1 LPTMR0_
ALT1
J11 52 RESET_b RESET_b RESET_b
G11 53 PTB0/
LLWU_P5
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL FTM1_CH0 FTM1_QD_
PHA
G10 54 PTB1 ADC0_SE9/
ADC1_SE9/
TSI0_CH6
ADC0_SE9/
ADC1_SE9/
TSI0_CH6
PTB1 I2C0_SDA FTM1_CH1 FTM1_QD_
PHB
G9 55 PTB2 ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
PTB2 I2C0_SCL UART0_RTS_
b
FTM0_FLT3
G8 56 PTB3 ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
PTB3 I2C0_SDA UART0_CTS_
b/
UART0_COL_
b
FTM0_FLT0
F11 — PTB6 ADC1_SE12 ADC1_SE12 PTB6 FB_AD23
E11 — PTB7 ADC1_SE13 ADC1_SE13 PTB7 FB_AD22
D11 — PTB8 DISABLED PTB8 UART3_RTS_
b
FB_AD21
E10 57 PTB9 DISABLED PTB9 SPI1_PCS1 UART3_CTS_
b
FB_AD20
D10 58 PTB10 ADC1_SE14 ADC1_SE14 PTB10 SPI1_PCS0 UART3_RX FB_AD19 FTM0_FLT1
C10 59 PTB11 ADC1_SE15 ADC1_SE15 PTB11 SPI1_SCK UART3_TX FB_AD18 FTM0_FLT2
— 60 VSS VSS VSS
— 61 VDD VDD VDD
B10 62 PTB16 TSI0_CH9 TSI0_CH9 PTB16 SPI1_SOUT UART0_RX FB_AD17 EWM_IN
E9 63 PTB17 TSI0_CH10 TSI0_CH10 PTB17 SPI1_SIN UART0_TX FB_AD16 EWM_OUT_b
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
219
General Business Information