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10.4.1 Core Modules
Table 10-2. JTAG Signal Descriptions
Chip signal name Module signal
name
Description I/O
JTAG_TMS JTAG_TMS/
SWD_DIO
JTAG Test Mode Selection I/O
JTAG_TCLK JTAG_TCLK/
SWD_CLK
JTAG Test Clock I
JTAG_TDI JTAG_TDI JTAG Test Data Input I
JTAG_TDO JTAG_TDO/
TRACE_SWO
JTAG Test Data Output O
JTAG_TRST JTAG_TRST_b JTAG Reset I
Table 10-3. SWD Signal Descriptions
Chip signal name Module signal
name
Description I/O
SWD_DIO JTAG_TMS/
SWD_DIO
Serial Wire Data I/O
SWD_CLK JTAG_TCLK/
SWD_CLK
Serial Wire Clock I
Table 10-4. TPIU Signal Descriptions
Chip signal name Module signal
name
Description I/O
TRACE_CLKOUT TRACECLK Trace clock output from the ARM CoreSight debug block O
TRACE_D[3:2] TRACEDATA Trace output data from the ARM CoreSight debug block used for 5-
pin interface
O
TRACE_D[1:0] TRACEDATA Trace output data from the ARM CoreSight debug block used for
both 5-pin and 3-pin interfaces
O
TRACE_SWO JTAG_TDO/
TRACE_SWO
Trace output data from the ARM CoreSight debug block over a
single pin
O
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
225
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