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10.4.4 Memories and Memory Interfaces
Table 10-9. EzPort Signal Descriptions
Chip signal name Module signal
name
Description I/O
EZP_CLK EZP_CK EzPort Clock Input
EZP_CS EZP_CS EzPort Chip Select Input
EZP_DI EZP_D EzPort Serial Data In Input
EZP_DO EZP_Q EzPort Serial Data Out Output
Table 10-10. FlexBus Signal Descriptions
Chip signal name Module signal
name
Description I/O
CLKOUT FB_CLK O FlexBus
Clock
Output
FB_AD[31:0]
1
FB_D31–FB_D0 Data Bus—During the first cycle, this bus drives the upper address
byte, addr[31:24].
When FlexBus is used in a nonmultiplexed configuration, this is the
data bus, FB_D. When FlexBus is used in a multiplexed
configuration, this is the address and data bus, FB_AD.
The number of byte lanes carrying the data is determined by the
port size associated with the matching chip-select.
When FlexBus is used in a multiplexed configuration, the full 32-bit
address is driven on the first clock of a bus cycle (address phase).
After the first clock, the data is driven on the bus (data phase).
During the data phase, the address is driven on the pins not used
for data. For example, in 16-bit mode, the lower address is driven
on FB_AD15–FB_AD0, and in 8-bit mode, the lower address is
driven on FB_AD23–FB_AD0.
I/O
FB_CS[5:0]
2
FB_CS5–FB_CS0 General Purpose Chip-Selects—Indicate which external memory or
peripheral is selected. A particular chip-select is asserted when the
transfer address is within the external memory's or peripheral's
address space, as defined in CSAR[BA] and CSMR[BAM].
O
FB_BE31_24_BLS7_
0,
FB_BE23_16_BLS15
_8,
FB_BE15_8_BLS23_
16,
FB_BE7_0_BLS31_2
4
3
FB_BE_31_24
FB_BE_23_16
FB_BE_15_8
FB_BE_7_0
Byte Enables—Indicate that data is to be latched or driven onto a
specific byte lane of the data bus. CSCR[BEM] determines if these
signals are asserted on reads and writes or on writes only.
For external SRAM or flash devices, the FB_BE outputs should be
connected to individual byte strobe signals.
O
FB_OE FB_OE Output Enable—Sent to the external memory or peripheral to
enable a read transfer. This signal is asserted during read accesses
only when a chip-select matches the current address decode.
O
FB_R W FB_R/W Read/Write—Indicates whether the current bus operation is a read
operation (FB_R/W high) or a write operation (FB_R/W low).
O
Table continues on the next page...
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
227
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