Information

Table 10-10. FlexBus Signal Descriptions
(continued)
Chip signal name Module signal
name
Description I/O
FB_TA
4
FB_TA Transfer Acknowledge—Indicates that the external data transfer is
complete. When FB_TA is asserted during a read transfer, FlexBus
latches the data and then terminates the transfer. When FB_TA is
asserted during a write transfer, the transfer is terminated.
If auto-acknowledge is disabled (CSCR[AA] = 0), the external
memory or peripheral drives FB_TA to terminate the transfer. If
auto-acknowledge is enabled (CSCR[AA] = 1), FB_TA is generated
internally after a specified number of wait states, or the external
memory or peripheral may assert external FB_TA before the wait-
state countdown to terminate the transfer early. The chip deasserts
FB_CS one cycle after the last FB_TA is asserted. During read
transfers, the external memory or peripheral must continue to drive
data until FB_TA is recognized. For write transfers, the chip
continues driving data one clock cycle after FB_CS is deasserted.
The number of wait states is determined by CSCR or the external
FB_TA input. If the external FB_TA is used, the external memory or
peripheral has complete control of the number of wait states.
Note: External memory or peripherals should assert FB_TA only
while the FB_CS signal to the external memory or
peripheral is asserted.
The CSPMCR register controls muxing of FB_TA with other
signals. If auto-acknowledge is not used and CSPMCR
does not allow FB_TA control, FlexBus may hang.
I
FB_TBST FB_TBST Transfer Burst—Indicates that a burst transfer is in progress as
driven by the chip. A burst transfer can be 2 to 16 beats depending
on FB_TSIZ1–FB_TSIZ0 and the port size.
Note: When a burst transfer is in progress (FB_TBST = 0b), the
transfer size is 16 bytes (FB_TSIZ1–FB_TSIZ0 = 11b), and
the address is misaligned within the 16-byte boundary, the
external memory or peripheral must be able to wrap around
the address.
O
1. FB_AD[23:21] not available on 100-LQFP devices.
2. FB_CS3not available on 100-LQFP devices.
3. FB_BE7_0_BLS31_24not available on 100-LQFP devices.
4. FB_TAnotavailable on 100-LQFP devices.
10.4.5 Analog
Table 10-11. ADC 0 Signal Descriptions
Chip signal name Module signal
name
Description I/O
ADC0_DP3,
PGA0_DP,
ADC0_DP[1:0]
DADP3–DADP0 Differential Analog Channel Inputs I
Table continues on the next page...
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
229
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