Information

Section number Title Page
28.4.2 FlexNVM Description..................................................................................................................................604
28.4.3 Interrupts......................................................................................................................................................607
28.4.4 Flash Operation in Low-Power Modes........................................................................................................608
28.4.5 Functional Modes of Operation...................................................................................................................608
28.4.6 Flash Reads and Ignored Writes..................................................................................................................608
28.4.7 Read While Write (RWW)...........................................................................................................................609
28.4.8 Flash Program and Erase..............................................................................................................................609
28.4.9 Flash Command Operations.........................................................................................................................609
28.4.10 Margin Read Commands.............................................................................................................................616
28.4.11 Flash Command Description........................................................................................................................617
28.4.12 Security........................................................................................................................................................638
28.4.13 Reset Sequence............................................................................................................................................640
Chapter 29
External Bus Interface (FlexBus)
29.1 Introduction...................................................................................................................................................................643
29.1.1 Definition.....................................................................................................................................................643
29.1.2 Features........................................................................................................................................................643
29.2 Signal descriptions........................................................................................................................................................644
29.3 Memory Map/Register Definition.................................................................................................................................647
29.3.1 Chip Select Address Register (FB_CSARn)................................................................................................648
29.3.2 Chip Select Mask Register (FB_CSMRn)...................................................................................................649
29.3.3 Chip Select Control Register (FB_CSCRn).................................................................................................650
29.3.4 Chip Select port Multiplexing Control Register (FB_CSPMCR)................................................................653
29.4 Functional description...................................................................................................................................................654
29.4.1 Modes of operation......................................................................................................................................654
29.4.2 Address comparison.....................................................................................................................................655
29.4.3 Address driven on address bus.....................................................................................................................655
29.4.4 Connecting address/data lines......................................................................................................................655
29.4.5 Bit ordering..................................................................................................................................................655
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
23
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