Information

PORTx_PCRn field descriptions (continued)
Field Description
1100 Interrupt when logic one.
Others Reserved.
15
LK
Lock Register
0 Pin Control Register fields [15:0] are not locked.
1 Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
14–11
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
10–8
MUX
Pin Mux Control
Not all pins support all pin muxing slots. Unimplemented pin muxing slots are reserved and may result in
configuring the pin for a different pin muxing slot.
The corresponding pin is configured in the following pin muxing slot as follows:
000 Pin disabled (analog).
001 Alternative 1 (GPIO).
010 Alternative 2 (chip-specific).
011 Alternative 3 (chip-specific).
100 Alternative 4 (chip-specific).
101 Alternative 5 (chip-specific).
110 Alternative 6 (chip-specific).
111 Alternative 7 (chip-specific).
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
DSE
Drive Strength Enable
This bit is read only for pins that do not support a configurable drive strength.
Drive strength configuration is valid in all digital pin muxing modes.
0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
5
ODE
Open Drain Enable
This bit is read only for pins that do not support a configurable open drain output.
Open drain configuration is valid in all digital pin muxing modes.
0 Open drain output is disabled on the corresponding pin.
1 Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
4
PFE
Passive Filter Enable
This bit is read only for pins that do not support a configurable passive input filter.
Passive filter configuration is valid in all digital pin muxing modes.
0 Passive input filter is disabled on the corresponding pin.
1 Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. A low
pass filter of 10 MHz to 30 MHz bandwidth is enabled on the digital input path. Disable the passive
input filter when high speed interfaces of more than 2 MHz are supported on the pin.
3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Introduction
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
246
Preliminary
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