Information

12.2 Memory map and register definition
The SIM module contains many fields for selecting the clock source and dividers for
various module clocks. See the Clock Distribution chapter for more information,
including block diagrams and clock definitions.
NOTE
The SIM_SOPT1 and SIM_SOPT1CFG registers are located at
a different base address than the other SIM registers.
SIM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_7000 System Options Register 1 (SIM_SOPT1) 32 R/W See section 12.2.1/255
4004_7004 SOPT1 Configuration Register (SIM_SOPT1CFG) 32 R/W 0000_0000h 12.2.2/257
4004_8004 System Options Register 2 (SIM_SOPT2) 32 R/W 0000_1000h 12.2.3/258
4004_800C System Options Register 4 (SIM_SOPT4) 32 R/W 0000_0000h 12.2.4/260
4004_8010 System Options Register 5 (SIM_SOPT5) 32 R/W 0000_0000h 12.2.5/263
4004_8018 System Options Register 7 (SIM_SOPT7) 32 R/W 0000_0000h 12.2.6/264
4004_8024 System Device Identification Register (SIM_SDID) 32 R Undefined 12.2.7/266
4004_8028 System Clock Gating Control Register 1 (SIM_SCGC1) 32 R/W 0000_0000h 12.2.8/267
4004_802C System Clock Gating Control Register 2 (SIM_SCGC2) 32 R/W 0000_0000h 12.2.9/268
4004_8030 System Clock Gating Control Register 3 (SIM_SCGC3) 32 R/W 0000_0000h 12.2.10/269
4004_8034 System Clock Gating Control Register 4 (SIM_SCGC4) 32 R/W F010_0030h 12.2.11/270
4004_8038 System Clock Gating Control Register 5 (SIM_SCGC5) 32 R/W 0004_0182h 12.2.12/272
4004_803C System Clock Gating Control Register 6 (SIM_SCGC6) 32 R/W 4000_0001h 12.2.13/274
4004_8040 System Clock Gating Control Register 7 (SIM_SCGC7) 32 R/W 0000_0007h 12.2.14/277
4004_8044 System Clock Divider Register 1 (SIM_CLKDIV1) 32 R/W See section 12.2.15/278
4004_8048 System Clock Divider Register 2 (SIM_CLKDIV2) 32 R/W 0000_0000h 12.2.16/280
4004_804C Flash Configuration Register 1 (SIM_FCFG1) 32 R See section 12.2.17/281
4004_8050 Flash Configuration Register 2 (SIM_FCFG2) 32 R See section 12.2.18/283
4004_8054 Unique Identification Register High (SIM_UIDH) 32 R See section 12.2.19/284
4004_8058 Unique Identification Register Mid-High (SIM_UIDMH) 32 R See section 12.2.20/284
4004_805C Unique Identification Register Mid Low (SIM_UIDML) 32 R See section 12.2.21/285
4004_8060 Unique Identification Register Low (SIM_UIDL) 32 R See section 12.2.22/285
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
254
Preliminary
Freescale Semiconductor, Inc.
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