Information

SIM_SOPT2 field descriptions (continued)
Field Description
18
USBSRC
USB clock source select
Selects the clock source for the USB 48 MHz clock.
0 External bypass clock (USB_CLKIN).
1 MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the
SIM_CLKDIV2[USBFRAC, USBDIV] descriptions.
17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
PLLFLLSEL
PLL/FLL clock select
Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options.
0 MCGFLLCLK clock
1 MCGPLLCLK clock
15–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
TRACECLKSEL
Debug trace clock select
Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source.
0 MCGOUTCLK
1 Core/system clock
11
PTD7PAD
PTD7 pad drive strength
Controls the output drive strength of the PTD7 pin by selecting either one or two pads to drive it.
0 Single-pad drive strength for PTD7.
1 Double pad drive strength for PTD7.
10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9–8
FBSL
FlexBus security level
If flash security is enabled, then this field affects what CPU operations can access off-chip via the
FlexBus interface. This field has no effect if flash security is not enabled.
00 All off-chip accesses (instruction and data) via the FlexBus are disallowed.
01 All off-chip accesses (instruction and data) via the FlexBus are disallowed.
10 Off-chip instruction accesses are disallowed. Data accesses are allowed.
11 Off-chip instruction accesses and data accesses are allowed.
7–5
CLKOUTSEL
CLKOUT select
Selects the clock to output on the CLKOUT pin.
000 FlexBus CLKOUT
001 Reserved
010 Flash clock
011 LPO clock (1 kHz)
100 MCGIRCLK
101 RTC 32.768kHz clock
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
259
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