Information

SIM_SOPT2 field descriptions (continued)
Field Description
110 OSCERCLK0
111 Reserved
4
RTCCLKOUTSEL
RTC clock out select
Selects either the RTC 1 Hz clock or the 32.768kHz clock to be output on the RTC_CLKOUT pin.
0 RTC 1 Hz clock is output on the RTC_CLKOUT pin.
1 RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
3–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.4 System Options Register 4 (SIM_SOPT4)
Address: 4004_7000h base + 100Ch offset = 4004_800Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
FTM0TRG1SR
C
FTM0TRG0SR
C
0
FTM2CLKSEL FTM1CLKSEL FTM0CLKSEL
0
FTM2CH0SRC FTM1CH0SRC
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FTM2FLT0
0
FTM1FLT0
0
FTM0FLT2 FTM0FLT1 FTM0FLT0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_SOPT4 field descriptions
Field Description
31–30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29
FTM0TRG1SRC
FlexTimer 0 Hardware Trigger 1 Source Select
Selects the source of FTM0 hardware trigger 1.
0 PDB output trigger 1 drives FTM0 hardware trigger 1
1 FTM2 channel match drives FTM0 hardware trigger 1
28
FTM0TRG0SRC
FlexTimer 0 Hardware Trigger 0 Source Select
Selects the source of FTM0 hardware trigger 0.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
260
Preliminary
Freescale Semiconductor, Inc.
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