Information

SIM_SCGC2 field descriptions
Field Description
31–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
DAC0
DAC0 Clock Gate Control
This bit controls the clock gate to the DAC0 module.
0 Clock disabled
1 Clock enabled
11–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)
Address: 4004_7000h base + 1030h offset = 4004_8030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0 0
ADC1
0 0
FTM2
0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0 0 0 0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_SCGC3 field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
29–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27
ADC1
ADC1 Clock Gate Control
This bit controls the clock gate to the ADC1 module.
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
269
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