Information

SIM_SCGC3 field descriptions (continued)
Field Description
0 Clock disabled
1 Clock enabled
26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
24
FTM2
FTM2 Clock Gate Control
This bit controls the clock gate to the FTM2 module.
0 Clock disabled
1 Clock enabled
23–18
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16–13
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)
Address: 4004_7000h base + 1034h offset = 4004_8034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
1 0
VREF CMP
USBOTG
0
W
Reset
1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
UART3 UART2 UART1 UART0
0
I2C1 I2C0
1 0
CMT EWM
0
W
Reset
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
270
Preliminary
Freescale Semiconductor, Inc.
General Business Information