Information

SIM_SCGC4 field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
27–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20
VREF
VREF Clock Gate Control
This bit controls the clock gate to the VREF module.
0 Clock disabled
1 Clock enabled
19
CMP
Comparator Clock Gate Control
This bit controls the clock gate to the comparator module.
0 Clock disabled
1 Clock enabled
18
USBOTG
USB Clock Gate Control
This bit controls the clock gate to the USB module.
0 Clock disabled
1 Clock enabled
17–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
UART3
UART3 Clock Gate Control
This bit controls the clock gate to the UART3 module.
0 Clock disabled
1 Clock enabled
12
UART2
UART2 Clock Gate Control
This bit controls the clock gate to the UART2 module.
0 Clock disabled
1 Clock enabled
11
UART1
UART1 Clock Gate Control
This bit controls the clock gate to the UART1 module.
0 Clock disabled
1 Clock enabled
10
UART0
UART0 Clock Gate Control
This bit controls the clock gate to the UART0 module.
0 Clock disabled
1 Clock enabled
9–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
271
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