Information

SIM_SCGC5 field descriptions (continued)
Field Description
1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
0
LPTIMER
Low Power Timer Access Control
This bit controls software access to the Low Power Timer module.
0 Access disabled
1 Access enabled
12.2.13 System Clock Gating Control Register 6 (SIM_SCGC6)
Address: 4004_7000h base + 103Ch offset = 4004_803Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 1
RTC
0
ADC0
0
FTM1 FTM0
PIT PDB
USBDCD
0
CRC
0
W
Reset
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
I2S
0
SPI1 SPI0
0 0 0
FLEXCAN0
0
DMAMUX
FTFL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
SIM_SCGC6 field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
Reserved
This field is reserved.
This read-only field is reserved and always has the value 1.
29
RTC
RTC Access Control
This bit controls software access and interrupts to the RTC module.
0 Access and interrupts disabled
1 Access and interrupts enabled
28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27
ADC0
ADC0 Clock Gate Control
This bit controls the clock gate to the ADC0 module.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
274
Preliminary
Freescale Semiconductor, Inc.
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