Information

SIM_SCGC6 field descriptions (continued)
Field Description
0 Clock disabled
1 Clock enabled
26
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
25
FTM1
FTM1 Clock Gate Control
This bit controls the clock gate to the FTM1 module.
0 Clock disabled
1 Clock enabled
24
FTM0
FTM0 Clock Gate Control
This bit controls the clock gate to the FTM0 module.
0 Clock disabled
1 Clock enabled
23
PIT
PIT Clock Gate Control
This bit controls the clock gate to the PIT module.
0 Clock disabled
1 Clock enabled
22
PDB
PDB Clock Gate Control
This bit controls the clock gate to the PDB module.
0 Clock disabled
1 Clock enabled
21
USBDCD
USB DCD Clock Gate Control
This bit controls the clock gate to the USB DCD module.
0 Clock disabled
1 Clock enabled
20–19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18
CRC
CRC Clock Gate Control
This bit controls the clock gate to the CRC module.
0 Clock disabled
1 Clock enabled
17–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
I2S
I2S Clock Gate Control
This bit controls the clock gate to the I
2
S module.
0 Clock disabled
1 Clock enabled
Table continues on the next page...
Chapter 12 System Integration Module (SIM)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
275
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