Information

SIM_SCGC6 field descriptions (continued)
Field Description
14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13
SPI1
SPI1 Clock Gate Control
This bit controls the clock gate to the SPI1 module.
0 Clock disabled
1 Clock enabled
12
SPI0
SPI0 Clock Gate Control
This bit controls the clock gate to the SPI0 module.
0 Clock disabled
1 Clock enabled
11–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8–5
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
4
FLEXCAN0
FlexCAN0 Clock Gate Control
This bit controls the clock gate to the FlexCAN0 module.
0 Clock disabled
1 Clock enabled
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
DMAMUX
DMA Mux Clock Gate Control
This bit controls the clock gate to the DMA Mux module.
0 Clock disabled
1 Clock enabled
0
FTFL
Flash Memory Clock Gate Control
This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory
is clock gated, but entry into low power modes is blocked.
0 Clock disabled
1 Clock enabled
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
276
Preliminary
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