Information

SIM_CLKDIV1 field descriptions (continued)
Field Description
1001 Divide-by-10.
1010 Divide-by-11.
1011 Divide-by-12.
1100 Divide-by-13.
1101 Divide-by-14.
1110 Divide-by-15.
1111 Divide-by-16.
15–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)
Address: 4004_7000h base + 1048h offset = 4004_8048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
USBDIV
USBFRAC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_CLKDIV2 field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–1
USBDIV
USB clock divider divisor
This field sets the divide value for the fractional clock divider when the MCGFLLCLK/MCGPLLCLK clock is
the USB clock source (SOPT2[USBSRC] = 1).
Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
0
USBFRAC
USB clock divider fraction
This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK/
MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1).
Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
280
Preliminary
Freescale Semiconductor, Inc.
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