Information

• LVD (without POR) — 0x02
• VLLS mode wakeup due to RESET pin assertion — 0x41
• VLLS mode wakeup due to other wakeup sources — 0x01
• Other reset — a bit is set if its corresponding reset source
caused the reset
Address: 4007_F000h base + 0h offset = 4007_F000h
Bit 7 6 5 4 3 2 1 0
Read POR PIN WDOG 0 LOL LOC LVD WAKEUP
Write
Reset
1 0 0 0 0 0 1 0
RCM_SRS0 field descriptions
Field Description
7
POR
Power-On Reset
Indicates a reset has been caused by the power-on detection logic. Because the internal supply voltage
was ramping up at the time, the low-voltage reset (LVD) status bit is also set to indicate that the reset
occurred while the internal supply was below the LVD threshold.
0 Reset not caused by POR
1 Reset caused by POR
6
PIN
External Reset Pin
Indicates a reset has been caused by an active-low level on the external RESET pin.
0 Reset not caused by external reset pin
1 Reset caused by external reset pin
5
WDOG
Watchdog
Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by
disabling the watchdog.
0 Reset not caused by watchdog timeout
1 Reset caused by watchdog timeout
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
LOL
Loss-of-Lock Reset
Indicates a reset has been caused by a loss of lock in the MCG PLL. See the MCG description for
information on the loss-of-clock event.
0 Reset not caused by a loss of lock in the PLL
1 Reset caused by a loss of lock in the PLL
2
LOC
Loss-of-Clock Reset
Indicates a reset has been caused by a loss of external clock. The MCG clock monitor must be enabled
for a loss of clock to be detected. Refer to the detailed MCG description for information on enabling the
clock monitor.
Table continues on the next page...
Reset memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
288
Preliminary
Freescale Semiconductor, Inc.
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