Information

Section number Title Page
34.5.4 Low-Power mode operation.........................................................................................................................801
Chapter 35
Voltage Reference (VREFV1)
35.1 Introduction...................................................................................................................................................................803
35.1.1 Overview......................................................................................................................................................804
35.1.2 Features........................................................................................................................................................804
35.1.3 Modes of Operation.....................................................................................................................................805
35.1.4 VREF Signal Descriptions...........................................................................................................................805
35.2 Memory Map and Register Definition..........................................................................................................................806
35.2.1 VREF Trim Register (VREF_TRM)............................................................................................................806
35.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................807
35.3 Functional Description..................................................................................................................................................808
35.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................808
35.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................809
35.4 Initialization/Application Information..........................................................................................................................810
Chapter 36
Programmable Delay Block (PDB)
36.1 Introduction...................................................................................................................................................................811
36.1.1 Features........................................................................................................................................................811
36.1.2 Implementation............................................................................................................................................812
36.1.3 Back-to-back acknowledgment connections................................................................................................813
36.1.4 DAC External Trigger Input Connections...................................................................................................813
36.1.5 Block diagram..............................................................................................................................................813
36.1.6 Modes of operation......................................................................................................................................815
36.2 PDB signal descriptions................................................................................................................................................815
36.3 Memory map and register definition.............................................................................................................................815
36.3.1 Status and Control Register (PDBx_SC).....................................................................................................817
36.3.2 Modulus Register (PDBx_MOD).................................................................................................................819
36.3.3 Counter Register (PDBx_CNT)...................................................................................................................820
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
29
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