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Table 14-1. Power modes (continued)
Mode Description
VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all
stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low
leakage mode by powering down the internal logic. All system RAM contents are retained and I/O
states are held. FlexRAM contents are not retained. Internal logic states are not retained.
VLLS2 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all
stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low
leakage mode by powering down the internal logic and the system RAM2 partition. The system
RAM1 partition contents are retained in this mode. FlexRAM contents are not retained. Internal logic
states are not retained.
1
VLLS1 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all
stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low
leakage mode by powering down the internal logic and all system RAM. A 32-byte register file
(available in all modes) contents are retained and I/O states held. FlexRAM contents are not
retained. Internal logic states are not retained.
1. See the devices' chip configuration details for the size and location of the system RAM partitions.
14.3 Memory map and register descriptions
Details follow about the registers related to the system mode controller.
Different SMC registers reset on different reset types. Each register's description provides
details. For more information about the types of reset on this chip, refer to the Reset
section details.
SMC memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_E000 Power Mode Protection register (SMC_PMPROT) 8 R/W 00h 14.3.1/297
4007_E001 Power Mode Control register (SMC_PMCTRL) 8 R/W 00h 14.3.2/299
4007_E002 VLLS Control register (SMC_VLLSCTRL) 8 R/W 03h 14.3.3/300
4007_E003 Power Mode Status register (SMC_PMSTAT) 8 R 01h 14.3.4/301
14.3.1 Power Mode Protection register (SMC_PMPROT)
This register provides protection for entry into any low-power run or stop mode. The
enabling of the low-power run or stop mode occurs by configuring the Power Mode
Control register (PMCTRL).
The PMPROT register can be written only once after any system reset.
Chapter 14 System Mode Controller
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
297
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