Information

Section number Title Page
36.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................820
36.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................821
36.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................822
36.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................822
36.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................823
36.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn).................................................................823
36.3.10 DAC Interval n Register (PDBx_DACINTn)..............................................................................................824
36.3.11 Pulse-Out n Enable Register (PDBx_POEN)...............................................................................................824
36.3.12 Pulse-Out n Delay Register (PDBx_POnDLY)...........................................................................................825
36.4 Functional description...................................................................................................................................................825
36.4.1 PDB pre-trigger and trigger outputs.............................................................................................................825
36.4.2 PDB trigger input source selection..............................................................................................................827
36.4.3 DAC interval trigger outputs........................................................................................................................827
36.4.4 Pulse-Out's...................................................................................................................................................828
36.4.5 Updating the delay registers.........................................................................................................................829
36.4.6 Interrupts......................................................................................................................................................830
36.4.7 DMA............................................................................................................................................................830
36.5 Application information................................................................................................................................................831
36.5.1 Impact of using the prescaler and multiplication factor on timing resolution.............................................831
Chapter 37
FlexTimer Module (FTM)
37.1 Introduction...................................................................................................................................................................833
37.1.1 FlexTimer philosophy..................................................................................................................................833
37.1.2 Features........................................................................................................................................................834
37.1.3 Modes of operation......................................................................................................................................835
37.1.4 Block diagram..............................................................................................................................................836
37.2 FTM signal descriptions...............................................................................................................................................838
37.3 Memory map and register definition.............................................................................................................................838
37.3.1 Memory map................................................................................................................................................838
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
30
Preliminary
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