Information

Section number Title Page
37.6.2 Channel (n) Interrupt....................................................................................................................................963
37.6.3 Fault Interrupt..............................................................................................................................................963
Chapter 38
Periodic Interrupt Timer (PIT)
38.1 Introduction...................................................................................................................................................................965
38.1.1 Block diagram..............................................................................................................................................965
38.1.2 Features........................................................................................................................................................966
38.2 Signal description..........................................................................................................................................................966
38.3 Memory map/register description.................................................................................................................................967
38.3.1 PIT Module Control Register (PIT_MCR)..................................................................................................967
38.3.2 Timer Load Value Register (PIT_LDVALn)...............................................................................................968
38.3.3 Current Timer Value Register (PIT_CVALn).............................................................................................969
38.3.4 Timer Control Register (PIT_TCTRLn)......................................................................................................969
38.3.5 Timer Flag Register (PIT_TFLGn)..............................................................................................................970
38.4 Functional description...................................................................................................................................................971
38.4.1 General operation.........................................................................................................................................971
38.4.2 Interrupts......................................................................................................................................................972
38.4.3 Chained timers.............................................................................................................................................972
38.5 Initialization and application information.....................................................................................................................973
38.6 Example configuration for chained timers....................................................................................................................974
Chapter 39
Low-Power Timer (LPTMR)
39.1 Introduction...................................................................................................................................................................975
39.1.1 Features........................................................................................................................................................975
39.1.2 Modes of operation......................................................................................................................................975
39.2 LPTMR signal descriptions..........................................................................................................................................976
39.2.1 Detailed signal descriptions.........................................................................................................................976
39.3 Memory map and register definition.............................................................................................................................977
39.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)......................................................................977
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
33
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