Information

MCM_PLAMC field descriptions (continued)
Field Description
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present
17.2.3 Control Register (MCM_CR)
CR defines the arbitration and protection schemes for the two system RAM arrays.
NOTE
Bits 23-0 are undefined after reset.
Address: E008_0000h base + Ch offset = E008_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SRAMLWP
SRAMLAP
0
SRAMUWP
SRAMUAP Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved
Reserved
Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_CR field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
SRAMLWP
SRAM_L Write Protect
When this bit is set, writes to SRAM_L array generates a bus error.
29–28
SRAMLAP
SRAM_L arbitration priority
Table continues on the next page...
Chapter 17 Miscellaneous Control Module (MCM)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
347
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