Information

AXBS memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_4710 Control Register (AXBS_CRS7) 32 R/W 0000_0000h 18.2.2/354
4000_4800 Master General Purpose Control Register (AXBS_MGPCR0) 32 R/W 0000_0000h 18.2.3/356
4000_4900 Master General Purpose Control Register (AXBS_MGPCR1) 32 R/W 0000_0000h 18.2.3/356
4000_4A00 Master General Purpose Control Register (AXBS_MGPCR2) 32 R/W 0000_0000h 18.2.3/356
4000_4B00 Master General Purpose Control Register (AXBS_MGPCR3) 32 R/W 0000_0000h 18.2.3/356
4000_4C00 Master General Purpose Control Register (AXBS_MGPCR4) 32 R/W 0000_0000h 18.2.3/356
4000_4D00 Master General Purpose Control Register (AXBS_MGPCR5) 32 R/W 0000_0000h 18.2.3/356
4000_4E00 Master General Purpose Control Register (AXBS_MGPCR6) 32 R/W 0000_0000h 18.2.3/356
4000_4F00 Master General Purpose Control Register (AXBS_MGPCR7) 32 R/W 0000_0000h 18.2.3/356
18.2.1 Priority Registers Slave (AXBS_PRSn)
The priority registers (PRSn) set the priority of each master port on a per slave port basis
and reside in each slave port. The priority register can be accessed only with 32-bit
accesses. After the CRSn[RO] bit is set, the PRSn register can only be read; attempts to
write to it have no effect on PRSn and result in a bus-error response to the master
initiating the write.
No two available master ports may be programmed with the same priority level. Attempts
to program two or more masters with the same priority level result in a bus-error response
and the PRSn is not updated.
NOTE
The possible values for the PRSn fields depend on the number
of masters available on the device. See the device's chip
configuration details for the number of masters supported.
• If the device contains less than five masters, values 000–
011 are valid and writing other values results in an error.
• If the device contains n masters where n ≥ 5, values 0 to n-1
are valid and writing other values results in an error.
Address: 4000_4000h base + 0h offset + (256d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
M7
0
M6
0
M5
0
M4
W
Reset
* * * * * * * * * * * * * * * *
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
M3
0
M2
0
M1
0
M0
W
Reset
* * * * * * * * * * * * * * * *
Chapter 18 Crossbar Switch (AXBS)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
351
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