Information

18.2.3 Master General Purpose Control Register (AXBS_MGPCRn)
The MGPCR controls only whether the master’s undefined length burst accesses are
allowed to complete uninterrupted or whether they can be broken by requests from higher
priority masters. The MGPCR can be accessed only in Supervisor mode with 32-bit
accesses.
Address: 4000_4000h base + 800h offset + (256d × i), where i=0d to 7d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
AULB
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AXBS_MGPCRn field descriptions
Field Description
31–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2–0
AULB
Arbitrates On Undefined Length Bursts
Determines whether, and when, the crossbar switch arbitrates away the slave port the master owns when
the master is performing undefined length burst accesses.
000 No arbitration is allowed during an undefined length burst
001 Arbitration is allowed at any time during an undefined length burst
010 Arbitration is allowed after four beats of an undefined length burst
011 Arbitration is allowed after eight beats of an undefined length burst
100 Arbitration is allowed after 16 beats of an undefined length burst
101 Reserved
110 Reserved
111 Reserved
18.3 Functional Description
18.3.1 General operation
When a master accesses the crossbar switch the access is immediately taken. If the
targeted slave port of the access is available, then the access is immediately presented on
the slave port. Single-clock, or -zero-wait state, accesses are possible through the
crossbar. If the targeted slave port of the access is busy or parked on a different master
Functional Description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
356
Preliminary
Freescale Semiconductor, Inc.
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