Information

19.1.2 General operation
The peripherals connected to the peripheral bridge are modules that contain readable/
writable control and status registers. The system masters read and write these registers
through the peripheral bridge. The peripheral bridge generates the following as inputs to
the peripherals:
• Module enables
• The module address
• Transfer attributes
• Byte enables
• Write data
The peripheral bridge captures read data from the peripheral interface and drives it to the
crossbar switch.
The register maps of the peripherals are located on 4 KB boundaries. Each peripheral is
allocated one 4 KB block of the memory map.
The peripheral bridge memory map is illustrated as follows.
Addresses Description
Base + 0x000_0000 - 0x000_0FFF Module #0
Base + 0x000_1000 - 0x000_1FFF Module #1
... ...
Base + 0x007_F000 - 0x007_FFFF Module #127
19.2 Memory map/register definition
The peripheral bridge registers are 32-bit registers and can be accessed only in Supervisor
mode by trusted bus masters. Additionally, these registers must be read only from or
written to by a 32-bit aligned access. The peripheral bridge registers are mapped into the
PACR0 address space.
Two system clocks are required for read accesses, and three system clocks are required
for write accesses to the peripheral bridge registers.
NOTE
The number of fields and registers available depends on the
device-specific implementation of the peripheral bridge
module. See the chip configuration chapter for more
information.
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
364
Preliminary
Freescale Semiconductor, Inc.
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