Information

19.2.1 Master Privilege Register A (AIPSx_MPRA)
The MPRA specifies identical 4-bit fields defining the access-privilege level associated
with a bus master in the device to various peripherals. The register provides one field per
bus master.
NOTE
At reset, the default value loaded into the MPRA fields is
device-specific. See the chip configuration details for the value
of a particular device.
A register field that maps to an unimplemented master or peripheral behaves as read-
only-zero.
Each master is assigned depending on its connection to the crossbar switch master ports.
See device-specific chip configuration details for information about the master
assignments to these registers.
Address: Base address + 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
MTR0
MTW0
MPL0
0
MTR1
MTW1
MPL1
0
MTR2
MTW2
MPL2
0
MTR3
MTW3
MPL3
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0 0 0
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
AIPSx_MPRA field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
MTR0
Master Trusted For Read
Determines whether the master is trusted for read accesses.
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
366
Preliminary
Freescale Semiconductor, Inc.
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