Information

AIPSx_MPRA field descriptions (continued)
Field Description
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.
19
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
18
MTR3
Master Trusted For Read
Determines whether the master is trusted for read accesses.
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
17
MTW3
Master Trusted For Writes
Determines whether the master is trusted for write accesses.
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
16
MPL3
Master Privilege Level
Specifies how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.
15–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
19.2.2 Peripheral Access Control Register (AIPSx_PACRn)
Each of the peripherals has a 4-bit PACR[0: 127 ] field which defines the access levels
supported by the given module. Eight PACR fields are grouped together to form a 32-bit
PACR[A: P ] register:
• PACRA- P define the access levels for the 128 peripherals
The peripheral assignments to each PACR are defined by the memory map slot that the
peripherals are assigned. See the device's memory map details for the assignments for a
particular device.
NOTE
The reset value of PACR[A:D] is 0x4444_4444.
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
368
Preliminary
Freescale Semiconductor, Inc.
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