Information

The following table shows the top-level structure of PACRs.
Offset Register [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0]
0x20 PACRA PACR0 PACR1 PACR2 PACR3 PACR4 PACR5 PACR6 PACR7
0x24 PACRB PACR8 PACR9 PACR10 PACR11 PACR12 PACR13 PACR14 PACR15
0x28 PACRC PACR16 PACR17 PACR18 PACR19 PACR20 PACR21 PACR22 PACR23
0x2C PACRD PACR24 PACR25 PACR26 PACR27 PACR28 PACR29 PACR30 PACR31
0x30 Reserved
0x34 Reserved
0x38 Reserved
0x3C Reserved
0x40 PACRE PACR32 PACR33 PACR34 PACR35 PACR36 PACR37 PACR38 PACR39
0x44 PACRF PACR40 PACR41 PACR42 PACR43 PACR44 PACR45 PACR46 PACR47
0x48 PACRG PACR48 PACR49 PACR50 PACR51 PACR52 PACR53 PACR54 PACR55
0x4C PACRH PACR56 PACR57 PACR58 PACR59 PACR60 PACR61 PACR62 PACR63
0x50 PACRI PACR64 PACR65 PACR66 PACR67 PACR68 PACR69 PACR70 PACR71
0x54 PACRJ PACR72 PACR73 PACR74 PACR75 PACR76 PACR77 PACR78 PACR79
0x58 PACRK PACR80 PACR81 PACR82 PACR83 PACR84 PACR85 PACR86 PACR87
0x5C PACRL PACR88 PACR89 PACR90 PACR91 PACR92 PACR93 PACR94 PACR95
0x60 PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103
0x64 PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111
0x68 PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
0x6C PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127
Address: Base address + 20h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SP0 WP0 TP0
0
SP1 WP1 TP1
0
SP2 WP2 TP2
0
SP3 WP3 TP3
W
Reset
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SP4 WP4 TP4
0
SP5 WP5 TP5
0
SP6 WP6 TP6
0
SP7 WP7 TP7
W
Reset
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
AIPSx_PACRn field descriptions
Field Description
31
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
30
SP0
Supervisor Protect
Determines whether the peripheral requires supervisor privilege level for accesses. When this field is set,
the master privilege level must indicate the supervisor access attribute, and the MPR x [MPL n ] control
field for the master must be set. If not, access terminates with an error response and no peripheral access
initiates .
Table continues on the next page...
Chapter 19 Peripheral Bridge (AIPS-Lite)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
369
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