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DMA Channel #0
Trigger #2
Source #1
Source #2
Source #3
Always #1
DMA Channel #3
Always #y
Trigger #4
Source #x
Trigger #1
DMA Channel #1
Figure 20-19. DMA MUX triggered channels
The DMA channel triggering capability allows the system to "schedule" regular DMA
transfers, usually on the transmit side of certain peripherals, without the intervention of
the processor. This trigger works by gating the request from the peripheral to the DMA
until a trigger event has been seen. This is illustrated in the following figure.
DMA Request
Peripheral Request
Trigger
Figure 20-20. DMA MUX channel triggering: normal operation
After the DMA request has been serviced, the peripheral will negate its request,
effectively resetting the gating mechanism until the peripheral re-asserts its request AND
the next trigger event is seen. This means that if a trigger is seen, but the peripheral is not
requesting a transfer, then that trigger will be ignored. This situation is illustrated in the
following figure.
Functional description
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
386
Preliminary
Freescale Semiconductor, Inc.
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