Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_8034 Hardware Request Status Register (DMA_HRS) 32 R/W 0000_0000h 21.3.15/429
4000_8100 Channel n Priority Register (DMA_DCHPRI3) 8 R/W See section 21.3.16/432
4000_8101 Channel n Priority Register (DMA_DCHPRI2) 8 R/W See section 21.3.16/432
4000_8102 Channel n Priority Register (DMA_DCHPRI1) 8 R/W See section 21.3.16/432
4000_8103 Channel n Priority Register (DMA_DCHPRI0) 8 R/W See section 21.3.16/432
4000_8104 Channel n Priority Register (DMA_DCHPRI7) 8 R/W See section 21.3.16/432
4000_8105 Channel n Priority Register (DMA_DCHPRI6) 8 R/W See section 21.3.16/432
4000_8106 Channel n Priority Register (DMA_DCHPRI5) 8 R/W See section 21.3.16/432
4000_8107 Channel n Priority Register (DMA_DCHPRI4) 8 R/W See section 21.3.16/432
4000_8108 Channel n Priority Register (DMA_DCHPRI11) 8 R/W See section 21.3.16/432
4000_8109 Channel n Priority Register (DMA_DCHPRI10) 8 R/W See section 21.3.16/432
4000_810A Channel n Priority Register (DMA_DCHPRI9) 8 R/W See section 21.3.16/432
4000_810B Channel n Priority Register (DMA_DCHPRI8) 8 R/W See section 21.3.16/432
4000_810C Channel n Priority Register (DMA_DCHPRI15) 8 R/W See section 21.3.16/432
4000_810D Channel n Priority Register (DMA_DCHPRI14) 8 R/W See section 21.3.16/432
4000_810E Channel n Priority Register (DMA_DCHPRI13) 8 R/W See section 21.3.16/432
4000_810F Channel n Priority Register (DMA_DCHPRI12) 8 R/W See section 21.3.16/432
4000_9000 TCD Source Address (DMA_TCD0_SADDR) 32 R/W Undefined 21.3.17/433
4000_9004 TCD Signed Source Address Offset (DMA_TCD0_SOFF) 16 R/W Undefined 21.3.18/433
4000_9006 TCD Transfer Attributes (DMA_TCD0_ATTR) 16 R/W Undefined 21.3.19/434
4000_9008
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD0_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_9008
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD0_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_9008
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD0_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
4000_900C
TCD Last Source Address Adjustment
(DMA_TCD0_SLAST)
32 R/W Undefined 21.3.23/438
4000_9010 TCD Destination Address (DMA_TCD0_DADDR) 32 R/W Undefined 21.3.24/438
4000_9014
TCD Signed Destination Address Offset
(DMA_TCD0_DOFF)
16 R/W Undefined 21.3.25/439
4000_9016
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD0_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_9016 DMA_TCD0_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_9018
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD0_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_901C TCD Control and Status (DMA_TCD0_CSR) 16 R/W Undefined 21.3.29/442
4000_901E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD0_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
399
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