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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 72 MHz I/O number 66

Section number Title Page

45.3.9 Error and Status 1 register (CANx_ESR1)..................................................................................................1125

45.3.10 Interrupt Masks 1 register (CANx_IMASK1).............................................................................................1129

45.3.11 Interrupt Flags 1 register (CANx_IFLAG1)................................................................................................1130

45.3.12 Control 2 register (CANx_CTRL2).............................................................................................................1132

45.3.13 Error and Status 2 register (CANx_ESR2)..................................................................................................1135

45.3.14 CRC Register (CANx_CRCR).....................................................................................................................1136

45.3.15 Rx FIFO Global Mask register (CANx_RXFGMASK)..............................................................................1137

45.3.16 Rx FIFO Information Register (CANx_RXFIR).........................................................................................1138

45.3.17 Rx Individual Mask Registers (CANx_RXIMRn).......................................................................................1139

45.3.34 Message buffer structure..............................................................................................................................1140

45.3.35 Rx FIFO structure........................................................................................................................................1146

45.4 Functional description...................................................................................................................................................1148

45.4.1 Transmit process..........................................................................................................................................1149

45.4.2 Arbitration process.......................................................................................................................................1149

45.4.3 Receive process............................................................................................................................................1153

45.4.4 Matching process.........................................................................................................................................1155

45.4.5 Move process...............................................................................................................................................1160

45.4.6 Data coherence.............................................................................................................................................1161

45.4.7 Rx FIFO.......................................................................................................................................................1165

45.4.8 CAN protocol related features.....................................................................................................................1166

45.4.9 Clock domains and restrictions....................................................................................................................1173

45.4.10 Modes of operation details...........................................................................................................................1173

45.4.11 Interrupts......................................................................................................................................................1177

45.4.12 Bus interface................................................................................................................................................1177

45.5 Initialization/application information...........................................................................................................................1178

45.5.1 FlexCAN initialization sequence.................................................................................................................1178

K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012

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Freescale Semiconductor, Inc.

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