Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9056 DMA_TCD2_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_9058
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD2_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_905C TCD Control and Status (DMA_TCD2_CSR) 16 R/W Undefined 21.3.29/442
4000_905E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD2_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
4000_905E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD2_BITER_ELINKNO)
16 R/W Undefined 21.3.31/445
4000_9060 TCD Source Address (DMA_TCD3_SADDR) 32 R/W Undefined 21.3.17/433
4000_9064 TCD Signed Source Address Offset (DMA_TCD3_SOFF) 16 R/W Undefined 21.3.18/433
4000_9066 TCD Transfer Attributes (DMA_TCD3_ATTR) 16 R/W Undefined 21.3.19/434
4000_9068
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD3_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_9068
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD3_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_9068
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD3_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
4000_906C
TCD Last Source Address Adjustment
(DMA_TCD3_SLAST)
32 R/W Undefined 21.3.23/438
4000_9070 TCD Destination Address (DMA_TCD3_DADDR) 32 R/W Undefined 21.3.24/438
4000_9074
TCD Signed Destination Address Offset
(DMA_TCD3_DOFF)
16 R/W Undefined 21.3.25/439
4000_9076
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD3_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_9076 DMA_TCD3_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_9078
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD3_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_907C TCD Control and Status (DMA_TCD3_CSR) 16 R/W Undefined 21.3.29/442
4000_907E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD3_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
4000_907E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD3_BITER_ELINKNO)
16 R/W Undefined 21.3.31/445
4000_9080 TCD Source Address (DMA_TCD4_SADDR) 32 R/W Undefined 21.3.17/433
4000_9084 TCD Signed Source Address Offset (DMA_TCD4_SOFF) 16 R/W Undefined 21.3.18/433
4000_9086 TCD Transfer Attributes (DMA_TCD4_ATTR) 16 R/W Undefined 21.3.19/434
4000_9088
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD4_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_9088
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD4_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_9088
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD4_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
401
General Business Information