Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_908C
TCD Last Source Address Adjustment
(DMA_TCD4_SLAST)
32 R/W Undefined 21.3.23/438
4000_9090 TCD Destination Address (DMA_TCD4_DADDR) 32 R/W Undefined 21.3.24/438
4000_9094
TCD Signed Destination Address Offset
(DMA_TCD4_DOFF)
16 R/W Undefined 21.3.25/439
4000_9096
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD4_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_9096 DMA_TCD4_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_9098
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD4_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_909C TCD Control and Status (DMA_TCD4_CSR) 16 R/W Undefined 21.3.29/442
4000_909E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD4_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
4000_909E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD4_BITER_ELINKNO)
16 R/W Undefined 21.3.31/445
4000_90A0 TCD Source Address (DMA_TCD5_SADDR) 32 R/W Undefined 21.3.17/433
4000_90A4 TCD Signed Source Address Offset (DMA_TCD5_SOFF) 16 R/W Undefined 21.3.18/433
4000_90A6 TCD Transfer Attributes (DMA_TCD5_ATTR) 16 R/W Undefined 21.3.19/434
4000_90A8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD5_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_90A8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_90A8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD5_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
4000_90AC
TCD Last Source Address Adjustment
(DMA_TCD5_SLAST)
32 R/W Undefined 21.3.23/438
4000_90B0 TCD Destination Address (DMA_TCD5_DADDR) 32 R/W Undefined 21.3.24/438
4000_90B4
TCD Signed Destination Address Offset
(DMA_TCD5_DOFF)
16 R/W Undefined 21.3.25/439
4000_90B6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD5_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_90B6 DMA_TCD5_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_90B8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD5_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_90BC TCD Control and Status (DMA_TCD5_CSR) 16 R/W Undefined 21.3.29/442
4000_90BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD5_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
4000_90BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD5_BITER_ELINKNO)
16 R/W Undefined 21.3.31/445
4000_90C0 TCD Source Address (DMA_TCD6_SADDR) 32 R/W Undefined 21.3.17/433
4000_90C4 TCD Signed Source Address Offset (DMA_TCD6_SOFF) 16 R/W Undefined 21.3.18/433
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
402
Preliminary
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