Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_90C6 TCD Transfer Attributes (DMA_TCD6_ATTR) 16 R/W Undefined 21.3.19/434
4000_90C8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD6_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_90C8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD6_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_90C8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD6_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
4000_90CC
TCD Last Source Address Adjustment
(DMA_TCD6_SLAST)
32 R/W Undefined 21.3.23/438
4000_90D0 TCD Destination Address (DMA_TCD6_DADDR) 32 R/W Undefined 21.3.24/438
4000_90D4
TCD Signed Destination Address Offset
(DMA_TCD6_DOFF)
16 R/W Undefined 21.3.25/439
4000_90D6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD6_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_90D6 DMA_TCD6_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_90D8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD6_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_90DC TCD Control and Status (DMA_TCD6_CSR) 16 R/W Undefined 21.3.29/442
4000_90DE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD6_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
4000_90DE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD6_BITER_ELINKNO)
16 R/W Undefined 21.3.31/445
4000_90E0 TCD Source Address (DMA_TCD7_SADDR) 32 R/W Undefined 21.3.17/433
4000_90E4 TCD Signed Source Address Offset (DMA_TCD7_SOFF) 16 R/W Undefined 21.3.18/433
4000_90E6 TCD Transfer Attributes (DMA_TCD7_ATTR) 16 R/W Undefined 21.3.19/434
4000_90E8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD7_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_90E8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD7_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_90E8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD7_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
4000_90EC
TCD Last Source Address Adjustment
(DMA_TCD7_SLAST)
32 R/W Undefined 21.3.23/438
4000_90F0 TCD Destination Address (DMA_TCD7_DADDR) 32 R/W Undefined 21.3.24/438
4000_90F4
TCD Signed Destination Address Offset
(DMA_TCD7_DOFF)
16 R/W Undefined 21.3.25/439
4000_90F6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD7_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_90F6 DMA_TCD7_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_90F8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD7_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_90FC TCD Control and Status (DMA_TCD7_CSR) 16 R/W Undefined 21.3.29/442
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
403
General Business Information