Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9134
TCD Signed Destination Address Offset
(DMA_TCD9_DOFF)
16 R/W Undefined 21.3.25/439
4000_9136
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD9_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_9136 DMA_TCD9_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_9138
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD9_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_913C TCD Control and Status (DMA_TCD9_CSR) 16 R/W Undefined 21.3.29/442
4000_913E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD9_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
4000_913E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled) (DMA_TCD9_BITER_ELINKNO)
16 R/W Undefined 21.3.31/445
4000_9140 TCD Source Address (DMA_TCD10_SADDR) 32 R/W Undefined 21.3.17/433
4000_9144 TCD Signed Source Address Offset (DMA_TCD10_SOFF) 16 R/W Undefined 21.3.18/433
4000_9146 TCD Transfer Attributes (DMA_TCD10_ATTR) 16 R/W Undefined 21.3.19/434
4000_9148
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD10_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_9148
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD10_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_9148
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD10_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
4000_914C
TCD Last Source Address Adjustment
(DMA_TCD10_SLAST)
32 R/W Undefined 21.3.23/438
4000_9150 TCD Destination Address (DMA_TCD10_DADDR) 32 R/W Undefined 21.3.24/438
4000_9154
TCD Signed Destination Address Offset
(DMA_TCD10_DOFF)
16 R/W Undefined 21.3.25/439
4000_9156
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD10_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_9156 DMA_TCD10_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_9158
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD10_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_915C TCD Control and Status (DMA_TCD10_CSR) 16 R/W Undefined 21.3.29/442
4000_915E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD10_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
4000_915E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD10_BITER_ELINKNO)
16 R/W Undefined 21.3.31/445
4000_9160 TCD Source Address (DMA_TCD11_SADDR) 32 R/W Undefined 21.3.17/433
4000_9164 TCD Signed Source Address Offset (DMA_TCD11_SOFF) 16 R/W Undefined 21.3.18/433
4000_9166 TCD Transfer Attributes (DMA_TCD11_ATTR) 16 R/W Undefined 21.3.19/434
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
405
General Business Information