Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_9168
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD11_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_9168
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD11_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_9168
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD11_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
4000_916C
TCD Last Source Address Adjustment
(DMA_TCD11_SLAST)
32 R/W Undefined 21.3.23/438
4000_9170 TCD Destination Address (DMA_TCD11_DADDR) 32 R/W Undefined 21.3.24/438
4000_9174
TCD Signed Destination Address Offset
(DMA_TCD11_DOFF)
16 R/W Undefined 21.3.25/439
4000_9176
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD11_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_9176 DMA_TCD11_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_9178
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD11_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_917C TCD Control and Status (DMA_TCD11_CSR) 16 R/W Undefined 21.3.29/442
4000_917E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD11_BITER_ELINKYES)
16 R/W Undefined 21.3.30/444
4000_917E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD11_BITER_ELINKNO)
16 R/W Undefined 21.3.31/445
4000_9180 TCD Source Address (DMA_TCD12_SADDR) 32 R/W Undefined 21.3.17/433
4000_9184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) 16 R/W Undefined 21.3.18/433
4000_9186 TCD Transfer Attributes (DMA_TCD12_ATTR) 16 R/W Undefined 21.3.19/434
4000_9188
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD12_NBYTES_MLNO)
32 R/W Undefined 21.3.20/435
4000_9188
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD12_NBYTES_MLOFFNO)
32 R/W Undefined 21.3.21/435
4000_9188
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD12_NBYTES_MLOFFYES)
32 R/W Undefined 21.3.22/436
4000_918C
TCD Last Source Address Adjustment
(DMA_TCD12_SLAST)
32 R/W Undefined 21.3.23/438
4000_9190 TCD Destination Address (DMA_TCD12_DADDR) 32 R/W Undefined 21.3.24/438
4000_9194
TCD Signed Destination Address Offset
(DMA_TCD12_DOFF)
16 R/W Undefined 21.3.25/439
4000_9196
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD12_CITER_ELINKYES)
16 R/W Undefined 21.3.26/439
4000_9196 DMA_TCD12_CITER_ELINKNO 16 R/W Undefined 21.3.27/440
4000_9198
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD12_DLASTSGA)
32 R/W Undefined 21.3.28/441
4000_919C TCD Control and Status (DMA_TCD12_CSR) 16 R/W Undefined 21.3.29/442
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
406
Preliminary
Freescale Semiconductor, Inc.
General Business Information