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• An illegal setting in the transfer-control descriptor, or
• An illegal priority register setting in fixed-arbitration
• An error termination to a bus master read or write cycle
See the Error Reporting and Handling section for more details.
Address: 4000_8000h base + 4h offset = 4000_8004h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
VLD 0 ECX
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 CPE 0 ERRCHN SAE SOE DAE DOE NCE SGE SBE DBE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_ES field descriptions
Field Description
31
VLD
Logical OR of all ERR status bits
0 No ERR bits are set
1 At least one ERR bit is set indicating a valid error exists that has not been cleared
30–17
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
16
ECX
Transfer Cancelled
0 No cancelled transfers
1 The last recorded entry was a cancelled transfer by the error cancel transfer input
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
CPE
Channel Priority Error
0 No channel priority error
1 The last recorded error was a configuration error in the channel priorities . Channel priorities are not
unique.
13–12
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
11–8
ERRCHN
Error Channel Number or Cancelled Channel Number
The channel number of the last recorded error (excluding CPE errors) or last recorded error cancelled
transfer .
7
SAE
Source Address Error
0 No source address configuration error.
1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR
is inconsistent with TCDn_ATTR[SSIZE].
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
411
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