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21.3.4 Enable Error Interrupt Register (DMA_ EEI )
The EEI register provides a bit map for the 16 channels to enable the error interrupt
signal for each channel. The state of any given channel’s error interrupt enable is directly
affected by writes to this register; it is also affected by writes to the SEEI and CEEI. The
{S,C}EEI are provided so the error interrupt enable for a single channel can easily be
modified without the need to perform a read-modify-write sequence to the EEI register .
The DMA error indicator and the error interrupt enable flag must be asserted before an
error interrupt request for a given channel is asserted to the interrupt controller.
Address: 4000_8000h base + 14h offset = 4000_8014h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EEI15 EEI14 EEI13 EEI12 EEI11 EEI10
EEI9 EEI8 EEI7 EEI6 EEI5 EEI4 EEI3 EEI2 EEI1 EEI0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_EEI field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
EEI15
Enable Error Interrupt 15
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
14
EEI14
Enable Error Interrupt 14
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
13
EEI13
Enable Error Interrupt 13
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
12
EEI12
Enable Error Interrupt 12
0 The error signal for corresponding channel does not generate an error interrupt
1 The assertion of the error signal for corresponding channel generates an error interrupt request
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
415
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