Information

Section number Title Page
46.4.2 Serial Peripheral Interface (SPI) configuration............................................................................................1210
46.4.3 Module baud rate and clock delay generation.............................................................................................1214
46.4.4 Transfer formats...........................................................................................................................................1216
46.4.5 Continuous Serial Communications Clock..................................................................................................1221
46.4.6 Slave Mode Operation Constraints..............................................................................................................1223
46.4.7 Interrupts/DMA requests..............................................................................................................................1223
46.4.8 Power saving features..................................................................................................................................1226
46.5 Initialization/application information...........................................................................................................................1227
46.5.1 How to manage queues................................................................................................................................1227
46.5.2 Switching Master and Slave mode...............................................................................................................1228
46.5.3 Initializing Module in Master/Slave Modes.................................................................................................1228
46.5.4 Baud rate settings.........................................................................................................................................1228
46.5.5 Delay settings...............................................................................................................................................1229
46.5.6 Calculation of FIFO pointer addresses.........................................................................................................1230
Chapter 47
Inter-Integrated Circuit (I2C)
47.1 Introduction...................................................................................................................................................................1233
47.1.1 Features........................................................................................................................................................1233
47.1.2 Modes of operation......................................................................................................................................1234
47.1.3 Block diagram..............................................................................................................................................1234
47.2 I2C signal descriptions..................................................................................................................................................1235
47.3 Memory map and register descriptions.........................................................................................................................1235
47.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................1236
47.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................1237
47.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................1238
47.3.4 I2C Status register (I2Cx_S)........................................................................................................................1240
47.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................1241
47.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................1242
47.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................1243
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
42
Preliminary
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