Information

DMA_ERR field descriptions (continued)
Field Description
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
3
ERR3
Error In Channel 3
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
2
ERR2
Error In Channel 2
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
1
ERR1
Error In Channel 1
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
0
ERR0
Error In Channel 0
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
21.3.15 Hardware Request Status Register (DMA_ HRS )
The HRS provide s a bit map for the DMA channels, signaling the presence of a
hardware request for each channel. The hardware request status bits reflect the current
state of the register and qualified (via the ERQ fields) DMA request signals as seen by
the DMA’s arbitration logic. This view into the hardware request signals may be used for
debug purposes.
NOTE
These bits reflect the state of the request as seen by the
arbitration logic. Therefore, this status is affected by the ERQ
bits.
Address: 4000_8000h base + 34h offset = 4000_8034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
429
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