Information

Section number Title Page
47.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................1244
47.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................1244
47.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................1246
47.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1246
47.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1247
47.4 Functional description...................................................................................................................................................1247
47.4.1 I2C protocol.................................................................................................................................................1247
47.4.2 10-bit address...............................................................................................................................................1252
47.4.3 Address matching.........................................................................................................................................1254
47.4.4 System management bus specification........................................................................................................1254
47.4.5 Resets...........................................................................................................................................................1257
47.4.6 Interrupts......................................................................................................................................................1257
47.4.7 Programmable input glitch filter..................................................................................................................1259
47.4.8 Address matching wakeup...........................................................................................................................1260
47.4.9 DMA support...............................................................................................................................................1260
47.5 Initialization/application information...........................................................................................................................1261
Chapter 48
Universal Asynchronous Receiver/Transmitter (UART)
48.1 Introduction...................................................................................................................................................................1265
48.1.1 Features........................................................................................................................................................1265
48.1.2 Modes of operation......................................................................................................................................1267
48.2 UART signal descriptions.............................................................................................................................................1268
48.2.1 Detailed signal descriptions.........................................................................................................................1269
48.3 Memory map and registers............................................................................................................................................1270
48.3.1 UART Baud Rate Registers: High (UARTx_BDH)....................................................................................1280
48.3.2 UART Baud Rate Registers: Low (UARTx_BDL).....................................................................................1281
48.3.3 UART Control Register 1 (UARTx_C1).....................................................................................................1282
48.3.4 UART Control Register 2 (UARTx_C2).....................................................................................................1283
48.3.5 UART Status Register 1 (UARTx_S1)........................................................................................................1285
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
43
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