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21.3.16 Channel n Priority Register (DMA_DCHPRIn)
When fixed-priority channel arbitration is enabled (CR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel . The channel priorities
are evaluated by numeric value; for example, 0 is the lowest priority, 1 is the next
priority, then 2, 3, etc. Software must program the channel priorities with unique values.
Otherwise, a configuration error is reported. The range of the priority value is limited to
the values of 0 through 15 .
Address: 4000_8000h base + 100h offset + (1d × i), where i=0d to 15d
Bit 7 6 5 4 3 2 1 0
Read
ECP DPA
0
CHPRI
Write
Reset
0 0 0 0 * * * *
* Notes:
CHPRI field: See bit field description•
DMA_DCHPRIn field descriptions
Field Description
7
ECP
Enable Channel Preemption
0 Channel n cannot be suspended by a higher priority channel’s service request
1 Channel n can be temporarily suspended by the service request of a higher priority channel
6
DPA
Disable Preempt Ability
0 Channel n can suspend a lower priority channel
1 Channel n cannot suspend any channel, regardless of channel priority
5–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–0
CHPRI
Channel n Arbitration Priority
Channel priority when fixed-priority arbitration is enabled
NOTE: Reset value for the channel priority fields, CHPRI, is equal to the corresponding channel number
for each priority register, i.e., DCHPRI15[CHPRI] equals 0b1111.
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
432
Preliminary
Freescale Semiconductor, Inc.
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