Information

Address: 4000_8000h base + 1008h offset + (32d × i), where i=0d to 15d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
SMLOE
DMLOE
NBYTES
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
NBYTES
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
DMA_TCDn_NBYTES_MLOFFNO field descriptions
Field Description
31
SMLOE
Source Minor Loop Offset Enable
Selects whether the minor loop offset is applied to the source address upon minor loop completion.
0 The minor loop offset is not applied to the SADDR
1 The minor loop offset is applied to the SADDR
30
DMLOE
Destination Minor Loop Offset enable
Selects whether the minor loop offset is applied to the destination address upon minor loop completion.
0 The minor loop offset is not applied to the DADDR
1 The minor loop offset is applied to the DADDR
29–0
NBYTES
Minor Byte Transfer Count
Number of bytes to be transferred in each service request of the channel.
As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate
reads and writes perform until the minor byte transfer count has transferred. This is an indivisible operation
and cannot be halted; although, it may be stalled by using the bandwidth control field, or via preemption.
After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD
memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration
count is completed, additional processing is performed.
21.3.22 TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCDn_NBYTES_MLOFFYES)
TCD word 2 is defined as follows if:
• Minor loop mapping is enabled (CR[EMLM] = 1) and
• Minor loop offset enabled (SMLOE or DMLOE = 1)
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
436
Preliminary
Freescale Semiconductor, Inc.
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