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The occurrence of any error causes the eDMA engine to stop normal processing of the
active channel immediately (it goes to its error processing states and the transaction to the
system bus still has peipeline effect), and the appropriate channel bit in the eDMA error
register is asserted. At the same time, the details of the error condition are loaded into the
ES register. The major loop complete indicators, setting the transfer control descriptor
DONE flag and the possible assertion of an interrupt request, are not affected when an
error is detected. After the error status has been updated, the eDMA engine continues
operating by servicing the next appropriate channel. A channel that experiences an error
condition is not automatically disabled. If a channel is terminated by an error and then
issues another service request before the error is fixed, that channel executes and
terminates with the same error condition.
21.4.3 Channel preemption
Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit.
Channel preemption allows the executing channel’s data transfers to temporarily suspend
in favor of starting a higher priority channel. After the preempting channel has completed
all its minor loop data transfers, the preempted channel is restored and resumes
execution. After the restored channel completes one read/write sequence, it is again
eligible for preemption. If any higher priority channel is requesting service, the restored
channel is suspended and the higher priority channel is serviced. Nested preemption, that
is, attempting to preempt a preempting channel, is not supported. After a preempting
channel begins execution, it cannot be preempted. Preemption is available only when
fixed arbitration is selected.
A channel’s ability to preempt another channel can be disabled by setting
DCHPRIn[DPA]. When a channel’s preempt ability is disabled, that channel cannot
suspend a lower priority channel’s data transfer, regardless of the lower priority channel’s
ECP setting. This allows for a pool of low priority, large data-moving channels to be
defined. These low priority channels can be configured to not preempt each other, thus
preventing a low priority channel from consuming the preempt slot normally available to
a true, high priority channel.
21.4.4 Performance
This section addresses the performance of the eDMA module, focusing on two separate
metrics:
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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