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Table 21-296. TCD Control and Status fields
TCDn_CSR field
name
Description
START Control bit to start channel explicitly when using a software initiated DMA service (Automatically
cleared by hardware)
ACTIVE Status bit indicating the channel is currently in execution
DONE Status bit indicating major loop completion (cleared by software when using a software initiated
DMA service)
D_REQ Control bit to disable DMA request at end of major loop completion when using a hardware initiated
DMA service
BWC Control bits for throttling bandwidth control of a channel
E_SG Control bit to enable scatter-gather feature
INT_HALF Control bit to enable interrupt when major loop is half complete
INT_MAJ Control bit to enable interrupt when major loop completes
The following figure shows how each DMA request initiates one minor-loop transfer, or
iteration, without CPU intervention. DMA arbitration can occur after each minor loop,
and one level of minor loop DMA preemption is allowed. The number of minor loops in
a major loop is specified by the beginning iteration count (BITER).
DMA request
DMA request
DMA request
Minor loopMinor loopMinor loop
Major loop
Current major
loop iteration
count (CITER)
3
2
1
Source or destination memory
Figure 21-292. Example of multiple loop iterations
The following figure lists the memory array terms and how the TCD settings interrelate.
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 1.1, Dec 2012
Freescale Semiconductor, Inc.
Preliminary
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